In real-time video applications such as videoconferencing, it is desirable to minimize system latency. A real-time image resizer such as a fractional decimator operative to resize each image of a sequence of images—a video stream—by scaling the number of horizontal picture elements (pixels) in a line and the number of lines in each digitized image by a not necessarily integer number is a typical component in a video signal processing chain. Such a fractional decimator requires buffering that adds latency to the video signal processing chain. For example, a known approach to fractional decimation is to process rows of data to horizontally resize using interpolation, and then resize the horizontally resized data in the vertical direction. Such a structure normally requires intermediate buffering, e.g., frame buffering, and normally has the latency of a full frame because vertical resizing cannot commence until all lines of the horizontal data have been resized.
Needing to avoid such intermediate frame buffering has been previously addressed. Robert D. Turney and Chris H. Dick: “Real Time Image Rotation and Resizing, Algorithms and Implementation,” Xilinx, Inc., retrieved Jan. 3, 2007 at http://www.xilinx.com/products/logicore/dsp/rotation_resize.pdf, and U.S. Pat. No. 6,801,674 to Turney of Xilinx, Inc., San Jose, Calif. describe an arrangement (The “Turney arrangement”) wherein line buffers are used for storage of lines of pixel values for resizing. A first one of the line buffers receives input pixel values, and the line buffers are coupled in an ordered chain such that a line buffer receives pixel values from a previous line buffer in the ordering. The lines of pixel values are moved from one line buffer to the next line buffer as the pixel values are processed for resizing. For resizing, a vertical resizer, e.g., vertical decimator follows the line buffers, and a horizontal resizer, e.g., horizontal decimator follows the vertical resizer, e.g., vertical decimator. While the Turney arrangement is suitable for a chip, and in fact, the Turney article describes an FPGA (field programmable gate array) implementation, on a serial processor, the line buffers would be implemented as a FIFO (first in first out) buffer of lines of the input image width. The memory for such input can become large.